How does error correction keep computer data reliable?

Computers add redundant information to the data they store. When the data is read back, the system recalculates what that extra information should be and compares it with what was stored. A mismatch shows that a bit has changed, and a well-designed code can show which bit, so hardware can flip it back without the running program noticing. This is called error-correcting code, or ECC. [1] [2]

A University of Wisconsin handout explains that stored or transmitted data can have bits flip, either from a permanent fault such as broken hardware or from a transient condition. Transient, or soft, errors often occur in DRAM or on network links. The handout adds that as transistors shrink, errors become more common, and cosmic rays or alpha particles can change values held in chip circuitry. Micron similarly names electrical interference and background radiation as causes of single-bit flips. [3] [1]

The simplest redundancy is a second copy of each bit. That detects a single error but cannot say which copy is wrong, and it doubles the storage. A parity bit is cheaper: one extra bit per group of data bits makes the count of 1s odd or even, so any single error is detected, but still not corrected. [3]

Real codes use several parity bits, each covering a different subset of the data. Sandisk's description is that parity bits indicate whether the number of 1s in predefined subsets is odd or even. Decoding then flips a minimal number of bits until all those constraints are satisfied. The Wisconsin handout frames this through Hamming distance, the number of positions in which two words differ. If valid codewords are at least three bits apart, a single error can be corrected. At a distance of four, any single-bit error can be corrected and any two-bit error detected. That arrangement is called SECDED, for single error correction, double error detection. [4] [3]

ECC memory modules carry extra chips for the check bits. Per Kingston, the processor's memory controller generates the code when data is written and stores it with the data. On each read it recalculates the code and compares it with the stored value. Micron says the code is typically derived from a Hamming code algorithm. A single-bit error is corrected, while double-bit and larger errors are reported to the operating system or firmware. All of this happens in hardware with minimal latency. [2] [1]

Flash storage faces a different problem. Kingston explains that repeated program/erase cycles weaken NAND cells, so read errors, retention loss and read-disturb effects grow as a drive ages, especially with dense TLC and QLC flash. Modern SSD controllers use LDPC (low-density parity-check) codes, described as far more powerful than older BCH-based methods, along with techniques such as read-retry. Kingston contrasts this with memory ECC: memory ECC protects data in use, while SSD ECC preserves data across its time in storage. Unlike memory ECC, it is set by the controller and firmware, not chosen by the user. [2]

Sandisk quotes Dr. Sharon saying the goal is to use as little redundancy as possible, close to the information-theoretic Shannon limit, while keeping complexity and power use low. [4]